vliw

vliw

1. Via the schedule tool TMSCHED, DT is translated to a VLIW instruction for TRIMEDIA.

DT经过TMCC的指令调度工具tmsched被翻译为TriMedia处理器的VLIW指令。

2. The TriMedia processor is a Philips VLIW processor that targets multimedia embedded applications.

TriMedia芯片是飞利浦公司设计的一个针对高性能多媒体应用的DSP芯片。

3. Software bypass and fine-grained parallel scheduling on VLIW

VLIW上的软件旁路与细粒度并行调度

4. VLIW isn't a magic bullet, but it's the new wave in microprocessor design.

vliw不是什么有魔法的子弹，但它却是新一轮的微处理器设计方法。

5. VLIW has become the prevailing philosophy of microprocessor design, eclipsing older approaches such as RISC and complex instruction set computing (CISC).

VLIW已经成为一种具有优势的微处理器设计方法，开始侵蚀RISC（精简指令集计算）和CISC（复杂指令集计算）较陈旧的设计方法。

6. VLIW is the latest way to simplify processors.

VLIW是简化处理器的最新方法。

7. VLIW chips don't need most of the complex control circuitry that superscalar chips must use to coordinate parallel execution at runtime.

VLIW芯片不需要超级标量芯片为运行时协调并行处理所采用的复杂控制电路。

8. Also,VLIW chips combine two or more instructions into a single bundle or packet.

VLIW芯片把2个或更多的指令捆绑成单一的包。

9. VLIW Processor

VLlW处理器

10. A poor VLIW compiler will have a much greater negative impact on performance than would a poor RISC or CISC compiler.

一个差的VLIW编译器对（系统）性能的负面影响超过差的RISC或CISC编译器的影响。

11. A Method to Improve the Throughput of the Instruction Fetch Unit in SMT VLIW Processors

一种提高同时多线程VLIW处理器中取指单元吞吐率的方法

12. VLIW chips can cost less, burn less power and achieve significantly higher performance than comparable RISC and CISC chips.

与RISC和CISC芯片相比，VLIW芯片的成本低、功耗低、并能获得更高的性能。

13. However DT must provide dependent information to ensure the same semantic affinity between DT and VLIW assembler, then we make a dependence analysis for DT.

为了正确调度DT中的操作，DT必须提供相关性信息来保证转换后的VLIW指令与其具有相同的语义，因此我们针对DT做了相关性分析。

14. Within a few years,it's certain that at least some of your software will be running on VLIW chips.

今后几年中，至少你的部分软件肯定会运行在VLIW芯片上。

15. Judged by the result of experiments, this RF configuration is not only satisfied with the requirements of media processors, but also well applied to media processors with VLIW architecture.

从实验的结果可以看出，这种结构不仅能满足媒体处理器的目标要求，而且对VLIW结构的媒体处理器有重要的意义。

16. It realizes the automation of ascertaining mutually exclusive microoperations. It is applicable to those CISC or VLIW processors that may include dozens,hundreds or even more different microoperations.

可编程实现互斥微操作命令查找的自动化,适用于包含几十、上百或更多种不同微操作命令的CISC或VLIW处理器的微指令设计。

17. But as VLIW microprocessor absolutely depends on the compiler to implement parallelism, it is very important to design a efficient optimized compiler.

同时，由于VLIW完全由编译器静态调度来实现各个功能部件的并行执行，因此VLIW机器并行性能的发挥很大程度上依赖于编译器的设计和实现。

18. A new design method of register file for VLIW architecture DSP is suggested through analyzing the structure,components and functions of the register file.

在研究了基于VLIW体系结构DSP的特点基础上,通过对寄存器堆的组织结构、组成单元、功能实现等方面的分析,提出了该结构寄存器堆的设计方案。

19. A Multicore Processor Design Based on VLIW Architecture

基于VLIW体系结构的多核处理器设计

20. The Research and Design of Instruction Format Based on VLIW

基于VLIW的指令格式的研究与设计

21. In the design of microprogrammed processor, mostly VLIW or CISC processors, reduction of microcode ROM area is performance critical as long as such reduction does not lower the speed to an impermissible level.

大多数 CISC处理器和 VLIW处理器都采用微程序控制。

22. The models successfully map 2-order IIR filtering algorithm on TMS320C6X VLIW DSP.

对2阶IIR滤波算法在TMS320C6X上的映射建立了模型，并使用LINGO进行模型求解。

23. VLSI Implementation of an Embeded VLIW Application Specific Processor for Speech Compression

嵌入式超长指令语音压缩处理器的VLSI实现

24. The Very Long Instruction Word (VLIW) architecture is widely used for DSP.

摘要超长指令字是一种在DSP中广泛使用的架构。

25. EPIC (Explicitly Parallel InstructionComputing) is a new ILP technology taking advantages of bothsuperscalar and VLIW, it enhances the performance using bothhardware and software with synergy between them.

显式并行指令计算EPIC（Explicitly Parallel Instruction Computing）则是VLIW和超标量技术特点开发的新一代指令级并行处理技术，通过软硬件相互协作提高性能。

26. This paper presents a survey on SOC hardware architecture, VLIW architecture, the embedded software of SOC and methodology of software/hardware co-design.

本文综述了系统集成芯片的硬件构造、超长指令（VLIW）结构、芯片嵌入软件及软硬件协同设计方法。

27. In this thesis, the author first presents the main content of code-optimizing and the chief task in VLIW compiler.And then some key technology used in architecture-dependent code-optimizing of VLIW.

本文首先介绍了代码优化的主要内容和VLIW编译优化的主要任务，进而介绍了当前VLIW优化编译器中被广泛应用的与体系结构相关的优化技术。

28. New DCT Computation Algorithm for VLIW Architecture

用超长指令实现DCT的新算法

29. Instead, VLIW chips shift more of that burden onto compilers.

相反，VLIW芯片将此负担的大部分转交给了编译器。

30. Combined the ISS with an assembler and a debugger,a software optimization development environment for block cipher specific VLIW processor is constructed.

结合指令集模拟器、汇编器以及调试器,设计了一个面向VLIW处理器的辅助程序优化环境。

31. The chip uses reconfigurable architecture and VLIW(very long instruction word) system design method, by which high complexity sub programs are optimized to get a remarkable instructions parallel.

芯片使用可重构体系结构和超长指令字系统设计方法,将复杂度高的子程序进行优化,能够显著提高指令并行度。

32. The chip uses a reconfigurable architecture and very long instruction words （VLIW） to optimize the complex functions.

芯片使用可重构体系结构和超长指令字（VLIW），优化了高复杂度函数。

33. This paper analyzes the relation problems about affecting VLIW exploiting ILP and presents some methods.

该文简要分析了影响VLIW指令级并行性发挥的控制相关问题,提出了相应的解决方法。

34. Very Long Instruction Word(VLIW)

超长指令字

35. Keywords VLIW;DSP;micro-architecture;Low power;Design for Test;Clock gate;prototype;

超长指令字;DSP;微体系结构;低功耗;可测试设计;门控;原型;

36. VLIW? Very Long Instruction Word?

超长指令字?

37. The Design of Shared Register File for VLIW DSP Processors

超长指令字DSP处理器的共享寄存器堆设计

38. VLIW Microprocessors

超长指令字微处理器

39. VLIW computer

超长指令字计算机

40. very long instruction word (VLIW)

超长指令字（VLIW）

41. VLIW microprocessor is now applied abroad in DSP field.

超长指令字（VLIW）结构在DSP处理器中得到越来越广泛的应用。

42. The state will persist until the buggy VLIW Transmeta code is flushed from the cache.

这种状态会持续到老出错误的VLIW Transmeta的代码被从缓冲器中移去。

43. Verification Strategy for DSP in VLIW Architecture

适用于VLIW数字信号处理器的功能验证策略

44. A 9-stage pipelined DSP with VLIW architecture is verified by this verification system, and the statement coverage c...

采用该平台对一个九级流水线的超长指令字结构数字信号处理器进行验证,可以在4000条指令内达到99%以上的代码语句覆盖率。

45. A 9-stage pipelined DSP with VLIW architecture is verified by this verification system, and the statement coverage can attain up to 99.9% within 4000 vectors.

采用该平台对一个九级流水线的超长指令字结构数字信号处理器进行验证，可以在4000条指令内达到99%以上的代码语句覆盖率。

46. Based on a C compiler system of a specified VLIW DSP, the author proposes a strategy of code-optimizing on assembler.

针对一个特定的DSP处理器的C编译系统，提出了一种对汇编代码的优化策略。