vlsi

vlsi

1. PC/104 embed system has mini-type dimension, same signal corresponded with PC/AT bus, and share functions that allow HCT and VLSI CMOS chip to drive and interrupt directly.

104嵌入式系统具有微型尺寸、与PC/AT总线对应信号相同，允许HCT逻辑和多数VLSI芯片直接驱动和中断共享等功能。

2. Computers built after 1972 are often called "fourth generation" computers, based on LSI (Large Scale Integration) of circuits. Later developments include VLSI (Very Large Scale Integration).

1972年以后的计算机习惯上被称为第四代计算机。基于大规模集成电路，及后来的超大规模集成电路。

3. The AMEX algorithm also features a modular structure which is well suitable for the parallel VLSI implementation.

AMEX算法具有高度的模块化结构，十分适合于VLSI实现。

4. Moreover, the BFM function can provide the potential of parallel VLSI implementation.

BFM函数便于并行实现,从而可以有效地缩短视频编码器的编码时间。

5. The coefficients of BT 7/5 filters are rational numbers, compared to CDF 9/7 filters with irrational coefficients, and they not only have advantage of easy computation but also are very suitable for implementation of VLSI hardware.

BT7/5小波的系数为有理数,与无理系数的CDF9/7小波滤波器相比,具有计算复杂度低和便于VLSI硬件实现等优点.

6. CMOS technics is mainstream technics in VLSI, which owes high integration and integrates many functions into one chip. Only one chip can complete full electric functions.

CMOS工艺是超大规模集成电路的主流工艺，集成度高，可以根据需要将多种功能集成在一块芯片上，单芯片就可以完成摄像机全部功能。

7. VLSI Implementation of Fast Algorithms for DCT

DCT快速算法及其VLSI实现

8. The DDM-CM Theory and Its Application in VLSI

DDM-CM理论及其在VLSI中的应用

9. JTAG is the test technology of IEEE specification.Its implementation reduces the complexity of the testing and is suitable for VLSI testing.

JTAG是符合IEEE规范的测试技术，JTAG的设计实现了测试复杂度的降低，适合进行大规模集成电路的测试。

10. The characteristic of MVP is the conversion from netlist to weighted undirected graph and its objective is to improve the efficiency of VLSI partitioner by avoiding partitioning netlist directly.

MVP系统特点体现在VLSI线网到无向赋权图的转换，避免了剖分算法直接在VLSI线网上进行剖分，提高了VLSI剖分的效率。

11. PC/104 embed system has mini-type dimension, same signal corresponded with PC/AT bus,and share functions that allow HCT and VLSI CMOS chip to drive and interrupt directly.

PC/104嵌入式系统具有微型尺寸、与PC/AT总线对应信号相同,允许HCT逻辑和多数VLSI芯片直接驱动和中断共享等功能。

12. Hierarchical DFT for VLSI and Electronic System

VLSI与电子系统的层次化可测性设计

13. Multivalued logic method for power estimation in VLSI[C]//Proceedings of the 14th Chinese Institute of Electronics Symposium on Circuits and Systems.Xiamen:1998:70-77.

VLSI功耗估计中的多值逻辑方法[C]//中国电子学会电路与系统学会第十四届年会论文集.厦门:1998:70-77.

14. VLSI and Application Specific Integrated Circuit ?

vlsi原理与专用集成电路设计

15. Metallization Technologies in VLSI

VLSI技术中的金属化工艺

16. The Research on Fluorinated Carbon Film for VLSI

VLSI用低介电常数含氟碳膜研究

17. Functional Test Generation for VLSI Circuit

VLSI电路功能测试码的生成

18. VLSI Design, Test and Electronic Design Automation

VLSI设计与测试及电子设计自动化

19. Emerging trends in VLSI test and diagnosis

VLSI超大规模集成电路测试和验证的发展趋势

20. A larger market leads to mass production, economies of scale in manufacturing, VLSI implementations, and other benefits that decrease price and further increase acceptance.

一个更大的市场带来大规模的生产、制造业的规模经济、超大规模集成电路实现等等一系列可以降低成本、曾加产品接受度的好处。

21. A VLSI Routing Algorithm with Minimum Time Delay

一种新的以时延优化为目标的布线算法研究

22. An improved algorithm for VLSI circuit partitioning

一类超大规模集成电路分割算法的改进

23. The scaling limit for gate oxide in VLSI is determined by the direct tunneling leakage current. Further device performance improvement can be obtained by using higher dielectric constant material.

中文摘要在深次微米时代,当元件愈做愈小,氧化层越来越薄时,漏电流增大的问题急需解决,而此时应用高介电材料的来取代传统氧化矽便愈发重要。

24. To make an economical solution possible ,coding should be realized using software (for a cheap and low-quality solution)or VLSI chips (for a high-quality solution).

为了实现经济电路VLSI芯片（对于高质量的解决方案）来实现。

25. A dispatching algorithm for VLSI processes is presented.Astrategy module an d a schedule module are cooperated to arrange process steps into equipment queue s.

介绍了一种用于VLSI制造业的生产调度算法，它包含一个策略部分和一个流程排序部分，二者协作实现实际工艺线的生产安排。

26. The background of commercial VLSI in military use is analyzed.

介绍了美、欧、日、韩今后发展超大规模集成电路的对策。

27. Estimating Power Consumption of CMOS VLSI Chip

估计CMOS VLSI芯片的功耗

28. But for the design of 64-bit stream processor, there are many challenges because of the limit of VLSI technology.

但是对于64位流处理器的设计，由于VLSI技术的限制，存在着很多挑战。

29. Low power design is playing a more and more important role in VLSI nowadays.

低功耗设计在当前超大规模集成电路中越来越重要.

30. Low power design is the most difficulties in DMB-H receiver core, and the key of its low power VLSI implementation is 3780 IFFT and QC-LDPC iterative decoder.

低功耗设计是DMB-H接收芯片面临的最大挑战，其中3780 IFFT和QC-LDPC信道译码是低功耗VLSI实现的关键。

31. This paper presents the general discussion about the development of current integration design methods, carefully introduces top down design method, hierarchy design method and embedded design method widely used in VLSI design.

全面综述了当前集成电路设计方法的发展 ,并详细地论述了当前超大规模集成电路系统设计中广泛采用的自顶向下、层次式和嵌入式设计方法。

32. Typical VLSI chips are 16 or 32 bit microprocessors, large capacity sorting machines, very large memories, or sophisticated devices used in communication equipment.

典型的超大规模的集成电路芯片，是用于16位或32位的微处理器、大容量分类设备、大容量存储设备，或者是用于通信的复杂设备上。

33. VLSI Clipper chips embodying EES would be used to encrypt data communications via telephone and ISDN lines.

内嵌EES的超大规模集成电路Clipper芯片可以用来对通过电话线和ISDN线的数据通信进行加密。

34. As a result, a method of VLSI (Very Large Scale Integration) implementation based on Integer Wavelet Transform (IWT) is proposed, thus high frame rates can be achieved with moderate gate complexity.

利用这个特性，提出了基于小波整数变换的VLSI实现，用适度的门复杂性来得到快速帧率。

35. Power optimization is the key technology of moden VLSI design.

功耗优化是现代VLSI设计的关键技术。

36. Power estimation is the first step towards implementing low-power design in VLSI systems.

功耗评估是进行低功耗研究的基础。

37. In addition, the algorithm can be realized high speed and low complexity VLSI circuits, without using multiplier, need only shifter, multiplexer and adder.

另外，该演算法已达成高速率和低复杂度的VLSI电路实现，不须要用到乘法器，仅须移位器、多工器和加法器。

38. J.D.Plummer, M. D.Deal and P.B.Griffin, “Silicon VLSI Technology,” Prentice Hall, 2000.

周卓明，“压电力学”，全华科技图书股分有限公司，民国92年。

39. So it's a real big breakthrough，” said Dan Hutcheson， head of VLSI Research， an industry consultancy.

因此，这无疑是一个巨大的突破。”

40. During VLSI test,the error caused by user's aid-hardware is always the key problem cumbering the precision and reliability of test and measurement.

在VLSI测试中，由于用户引入辅助硬件产生的误差问题,一直是阻碍测试精度和可靠性的关键问题。

41. The CMOS technology is the most promising technology for efficient VLSI implementation of a UWB transceiver because of its low cost, low power consumption, and high system level integration.

在低成本、低必v消耗以及高系统整合的优势之下，使用CMOS制程来实现超宽频接收机为最佳的选择。

42. Among clock network designs, the buffered clock tree architecture is the most popular clock network design adopted in modern VLSI designs.

在时钟网路的设计中，目前最普遍采用在现今晶片设计的是缓冲器式时钟树。

43. In this thesis, two edge-preserved image denoising methods and their VLSI implementations are presented: cost-effective denoising method and high performance one.

在本论文中，我们提出了一个能保留影像边缘特性的杂讯移除演算法及其硬体实作，并针对成本的考量，提供一个较低硬体成本的设计。

44. In VLSI design flow, design rule checking (DRC) is an important step.

在超大规模集成电路(VLSI)设计流程中,设计规则检查(DRC)是关键一环。

45. In the VLSI design cycle, in order to detect and debug the errors in early stages or to verify the functional correctness hierarchically, black boxing verification methods are often used.

在超大规模集成电路设计中 ,为了进行早期的设计错误检测与调试或层次化验证 ,常常需要使用含黑盒的设计验证方法 .

46. DRC Accelerated System of VLSI Based on GPU

基于GPU的VLSI的DRC加速系统

47. Large scale integration (LSI): Referring to high-performance chips, which incorporating more than 100 gates or more than 1000 components. See Very large scale integration (VLSI).

大规模集成电路:指高效能的晶片。它是100个门线路以上或100个元件以上的组合。参阅超大规模集成电路。

48. For most applications SSI, MSI, LSI and VLSI IC's are used to implement different parts of a circuit, connections between individual circuits are built using the pins on the IC's connected to one another with a printed circuit board.

大量的小型集成、中型集成电路、大规模集成电路和超大规模的集成电路被用在大规模电路的各个部分，这些电路被分别固定在相连的电路板上。

49. Her research interest is VLSI design.

她的研究兴趣是VLSI设计。

50. It details the IC design process and VLSI circuits, including gate arrays, programmable logic devices and arrays, parasitic capacitance, and transmission line delays.

它详细规定了集成电路设计过程和超大规模集成电路电路，包括门阵列，可编程逻辑器件和阵列，寄生电容，及输电线路的延误。

51. The experiment and analysis show that the multilevel partitioner of MVP can find the better partitioning and MVP can improve the performance of VLSI partitioner.

实验及分析表明MVP系统的多水平剖分程序能找到更优的图剖分，以及MVP系统找到比现有技术更优的VLSI剖分，提高了VLSI剖分的性能。

52. The experimental results show that the radiation sensitive switch is capable of driving very large scale integrated circuits(VLSI) successfully and achieving the goal of latchup prevention.

实验结果表明,该辐射敏感开关能够成功驱动超大规模集成电路,达到抗闭锁设计目的。

53. For VLSI, a plane surface may be approximated by depositing the interlevel dielectric by bias-sputter deposition (see Section 9. 2. 4) or by using planarization.

对于超大规模集成电路的平面状表面,可以用偏置溅射淀积法的层间介质淀积(见9.2.4节)或用平面化工艺来近似获得。

54. VLSI FLOORPLAN OPTIMIZATION DESIGN WITH SOFT BLOCKS

带软模块的VLSI布图规划优化设计

55. And, it is it utilize five piece it is Very Large Scale Integrated ( VLSI ) and two pieces of peripheral integrated circuit ( when pulse generator and power amplifier ) finish.

并且，是利用五个超大型积体电路(VLSI)及两个周边积体电路(时脉产生器和功率放大器)完成。

56. The establishment of the "Nantong City VLSI CMP polishing Engineering Research Center" and "Nantong City Technology Center.

建立了“南通市超大规模集成电路CMP抛光工程研究中心”和“南通市技术中心”。

57. The designed equalizer employing decision feedback structure can be applied for 64/256 QAM demodulation and easily realized by VLSI technology.

所设计的均衡器支持64/256的正交幅度解调且易于VLSI实现。

58. Abstract： The capability of cross-connection is one of the most important guide line in SDH.It greatly depends on the design of Very Large Scale Integration(VLSI) for cross-connect.

摘 要： 交叉连接能力是SDH系统的一项至关重要的功能指标，而交叉能力的强弱又完全依赖于交叉连接超大规模集成电路的能力。

59. Abstract： During VLSI test,the error caused by user's aid-hardware is always the key problem cumbering the precision and reliability of test and measurement.

摘 要： 在VLSI测试中，由于用户引入辅助硬件产生的误差问题,一直是阻碍测试精度和可靠性的关键问题。

60. Power supply quiescent current (IDDQ) testing has been very effective in VLSI circuits designed in CMOS processes detecting physical defects such as open and shorts and bridging defects.

摘要 本研究目的乃在发展一套大区域的非破坏检测的振波技术来找出管路中的缺陷或裂缝。

61. In deep sub-micron VLSI technologies, the interconnect delay has become a dominant factor affecting performance of ICs.

摘要:在深次微米积体电路技术中,连线延迟成为了影响IC晶片效能的主要因素。

62. In this paper, a VLSI architecture for carrier synchronization is proposed using DVB-H as an example.

摘要以DVB-H系统为例对载波同步算法提出了一种硬件实现架构。

63. A self-test scheme, under which all test patterns for adder under test in VLSI are produced by the adder self, is presented based on arithmetic additive generator.

摘要基于算术加法测试生成，提出了VLSI中加法器的一种自测试方案：加法器产生自身所需的所有测试矢量。

64. Because of its inherent weakness, the package failure of plastic encapsulated VLSI becomes one of the most important failure mode during its engineering application.

摘要塑封VLSI由于其固有的弱点，在应用过程中封装失效成为其重要的失效模式之一。

65. Methods of parameter extraction in VLSI layout verification are studied and a new resistance extractor based on a boundary element method is presented.

摘要总结了VLSI版图验证中提取电阻参数的各种方法的优缺点，给出了一种基于边界元法的电阻提取算法。

66. VLSI implementation of an image-reject filter for initial demodulator circuit used in QAM receiver chip for digital TV presented.

摘要提出一种用于接收数字电视信号的QAM解调芯片中，初始解调电路的镜像抑制滤波器的VLSI实现方法。

67. VLSI architecture for the implementation of image compression coding using pipeline and time division multiplexing technology in lifting wavelet transform and SPIHT was proposed.

摘要提出了一种基于提升小波变换和SPIHT算法的图像压缩编码的VLSI结构。

68. A novel divider based on dual-bit algorithm and its VLSI implementation are presented.

摘要提出了基于双比特算法的新型除法器及其VLSI实现结构。

69. This paper presented an innovative analytical delay model for RLC interconnects utilized in the estimation of interconnect delay for deep sub-micrometer VLSI circuits.

摘要提出了用来评估深亚微米VLSI电路中RLC互连延时的一种新的解析延时模型。

70. Testing analog/mixed-signal circuitry becomes more and more difficult due to the rapid advance of the VLSI technology.

摘要由于超大规模集成电路技术的快速进步，测试数模混合电路变得越来越困难。

71. Investigates the implementation scheme of cellular automata (CA) for application in the pseudo-random test of very large scale integration (VLSI) as a test pattern generator.

摘要研究细胞自动机(CA)在超大规模集成电路(VLSI)伪随机测试中作为测试激励的结构和实现方法。

72. The theory of rectilinear embeddings of graphs has been used in the design of VLSI.

摘要纵横嵌入的理论已被用在超大规模集成电路的设计中。

73. A method for threshold selection and decision to obtain noise characteristics in VLSI circuits was presented.

摘要给出了利用阈值选取和决策对VLSI电路噪声特性进行检测的方法。

74. The development trend of overseas VLSI and its function in military equipment are discussed The tactics of the developing VLSI technology of U.

摘要论述了国外超大规模集成电路的发展趋势及在武器装备中的作用。

75. The maximum problem of parametric yield in VLSI is always an important issue in design for manufacturing (DFM).

摘要超大规模集成电路(VLSI)中的参数成品率最优化问题一直是集成电路可制造性设计的重点研究问题。

76. As the process for design of VLSI enters deep submicron stage, the power dissipation caused by leakage current can not be neglected anymore.

摘要超大规模集成电路设计工艺已进入深亚微米阶段，漏电流功耗已经成为不可忽视的部分。

77. Boundary-scan technology (BST) is a new and effective way of test and design-for-testability (DFT) for VLSI circuits.

摘要边界扫描技术是一种新型的VLSI电路测试及可测性设计方法。

78. In this paper, a VLSI architecture for channel estimation and cyclic restoration in TDS-OFDM is proposed.The realization of cyclic correlation introduced is high-speed and low-cost.

摘要针对TDS-OFDM系统的信道估计与数据循环化算法提出了一种硬件实现架构，其中循环相关的实现架构速度快且节省硬件资源。

79. With the wide use of VLSI, the percentage of the open faults, bridging faults and stuck logic faults are rising in the complex PCB, and the testability of PCB is becoming more difficult.

摘要随著VLSI电路的广泛使用，复杂PCB板上的开路、桥接和固定逻辑故障的比例逐渐上升，可测试性明显下降。

80. Abstract: This paper presents the construction of the high and low temperature testing system of VLSI, as well as the main characteristics of the precision temperature farcing system and its practicability.

摘要：介绍了大规模集成电路高低温测试系统的建立，介绍了热流系统的主要技术指标和实用性。